sclk การใช้

Meanwhile, the controller feeds a clock called the " shift clock " ( SCLK ) to the VRAM's video port.
Each SCLK pulse causes the VRAM to deliver the next data bit, in strict address order, from the shift register to the video port.
All slave devices share the same SS ( Slave Select; active low ) line, along with the other three SPI signals : SCLK, MOSI and MISO . Additionally all slave devices normally have their MISO line disconnected from the bus in a high impedance state.